The present invention relates to semiconductor integrated circuits, and more particularly to a word line boosting circuit for supplying a constant voltage level word line signal and a control circuit therefor.
Generally, in a semiconductor integrated circuit such as a dynamic random access memory (DRAM), a memory cell consists of one access transistor and one storage capacitor. Data of a high "1" or low "0" voltage level, for example, is stored in the storage capacitor. The data stored in the storage capacitor is transferred to a bit line through the channel of the access transistor. The speed that the data is transferred to the bit line and the a voltage level of the signed transferred depend on the voltage level of a word line applied to the gate of the access transistor. With high integration density and larger capacity semiconductor memory integrated circuits, high speed operation is required. The highest integration density of the chip has led to the use of a lower operating supply voltage due to the reduction of the size of the transistor. With such a low supply voltage, the voltage level of the word line applied to the gate of the access transistor within the memory cell is not enough to transfer the data stored in the storage capacitor to the bit line using conventional voltage boosting circuitry. As a result, lower operating speeds and other disadvantages occur.
To overcome such problems, new voltage boosting circuits (also known as a boosting circuit or, more specifically a "word line boosting circuit") for generating a boosting voltage over a supply voltage within the chip have been proposed
FIGS. 1A and 1B illustrate block diagrams of prior art voltage boosting circuits. As shown in FIG. 1A, word line boosting circuit 1 utilizing a charge pumping provides a word line W/L voltage higher than a supply voltage Vcc. The boosting level is determined by a charge sharing ratio between a pumping capacitor (not shown) and the parasitic capacitance of the word line being enabled. If the size of the pumping capacitor is larger than that of the parasitic capacitance of the word line, the boosting level is raised. Therefore, the size of the pumping capacitor of the word line boosting circuit 1 should enable a voltage greater than Vcc+Vtn (VtN being the threshold voltage of the access transistor of the memory cell). If the size of the pumping capacitor is too large relative to the word line loading, the word line voltage becomes too high and excessive stress is applied to the access transistor, thereby shortening the life of the chip. On the other hand, if the size of the pumping capacitor is too small, the voltage of data line is not sufficiently transferred to the storage capacitator of the memory cell. Thus, when using the conventional word line boosting circuit, the loading of the word line should be constant to maintain a uniform word line level.
FIG. 1B shows a block diagram of a word line boosting circuit for a highly integrated semiconductor circuit. Two memory cell arrays 3A and 3B are connected to one word line boosting circuit 1, and the coding processes of row decoders 2A and 2B are different than with respect to FIG. 1(a) for selecting a word line enabled during a circuit operation. A single word line boosting circuit is used to boost the word line voltage of either a single memory cell array or two memory cell arrays. However, depending on how the word line boosting circuit is designed, operation characteristics will vary. If the word line boosting circuit is designed in considering word line loading when both array blocks 3A and 3B are enabled, the word line voltage is too high when only one array block is enabled, with the result that the excessive stress is applied and the life of a memory device is shortened. If the word line boosting circuit is designed considering the case when one array block is enable, the word line loading when one array block is enabled, a boosting voltage that is too small relative to the size of the pumping capacitor of the word line boosting circuit is generated when one array block is enabled, thereby lowering the word line voltage. Thus in such a word line boosting process, it is difficult to supply a stable word line voltage, and as a result, reliable operation of the semiconductor integrated circuit can not be realized.